The present disclosure relates to an electrostatic discharge (ESD) protection circuit, in particular, to an ESD protection circuit for a high voltage input pad.
Electrostatic discharge is an event that can occur during device fabrication, assembly packaging, or device handling. During a typical ESD event, a large amount of charges can accumulate in a bonding pad of an integrated circuit. If the charges produce a high voltage that a chip cannot tolerate, a fatal discharge may happen inside the chip to cause the chip malfunction. It is therefore important for semiconductor chips to have protection mechanisms against ESD events.
In the past, nominal operating voltage was usually 5 volts for semiconductor chips and for electronic devices using the semiconductor chips. Due to the advances in semiconductor processing technologies, nowadays the operating voltages for the semiconductor chips are commonly at 1.8 volts or even as low as 1.0 volt. The breakdown voltages for gate-to-drain, gate-to-source, and drain-to-source in transistors have all come down rapidly in recent years. The maximum transistor operation voltage for transistors is about 6.0-6.5 volt for 0.35 micron semiconductor fabrication and 4.0-4.5 volt for 0.18 micron semiconductor fabrication. However, these voltages can only operate in a short time and prolonged operation will reduce transistor's reliability. Therefore, operating voltage range for typical 0.35 um is 2.7V-3.6V and 1.6V-2.0V for 0.18 um. Transistors' breakdown voltages are likely to continue to trend downwards in the foreseeable future.
Electronic devices that use semiconductor chips, on the other hand, have not kept up with the pace of advancement by the semiconductor processing technologies. Nominal operating voltages for most electronic devices are still in the range of 3.3 volts and 5.0 volts. The gap between the nominal operating voltages for semiconductor chips and electronic devices require that the semiconductor chips to handle high-voltage inputs to the chips from the rest of the electronic devices.
FIG. 1 disclosed a conventional ESD protection circuit 10 that includes NMOS (i.e. N-MOSFET) transistors 101 and 102 connected in a cascoded or series configuration. The gate of the transistor 101 connected to a high-voltage supply terminal (VDD). The gate of transistor 102 is connected to its source to form a diode-connected transistor. The source of the transistor 102 is connected to a low-voltage supply terminal (VSS).
The ESD protection circuit 10 can protect the circuit 105 from high voltage input as the input/output (IO) pad 100. Assuming the ESD protection circuit 10 is fabricated using 0.35 micron semiconductor fabrication technologies, the maximum transistor operation voltage for the transistors is about 6.0V. VDD is typically at 3.3V. The drain of the NMOS transistor 101 is connected with an IO pad 100 that can receive a high voltage inputs from the rest of the electronic device. For example, for a one-time-program (OTP) device, the memory programming voltage is at about 6.5V. The drain-to-gate voltage (VDS) is thus 6.5V −3.3V=3.2V. The source voltage is VDD−VTN (assuming VTN=1.0V)=2.3V, wherein VTN is the turn-on threshold voltage for a NMOS transistor. The drain-to-source voltage for the transistor 101 is 6.5V−2.3V=4.2V. The voltage differences between the three terminals of the transistor 101 are therefore all below the maximum transistor operation voltage of 6.0V for transistors using 0.35 micron semiconductor fabrication technologies.
A major drawback exists, however, in the ESD protection circuit 10. During ESD event zapping from the IO pad 100 to VSS (i.e., VSS connects to ground), the gate voltage for the transistor 101 is undefined, which can affect the current shunting performance of both transistors 101 and 102. During ESD event zapping from the IO pad 100 to VDD (i.e., VDD connects to ground), the gate of transistor 101 is shorted to the ground. No current shunting can occur in the drain-to-source current path. As a result, the ESD protection circuit 10 can only protect the circuit 105 from high voltage input at the IO pad 100 but cannot provide proper protection against ESD events.
Another conventional ESD protection circuit 20, referring to FIG. 2, includes an improvement over the ESD protection circuit 10. A parasitic diode 120 added between the IO pad 100 and VDD can improve current discharging for an ESD event that zaps from IO pad to VDD. The ESD protection circuit 20, however, cannot properly handle high voltage input at the IO pad 100. When an input signal at 6.5V is applied to the IO pad 100, current leakage can occur from the IO pad 100 to VDD if the voltage between the IO pad 100 and the VDD is higher than the diode bias voltage that is normally around 1.0 V. For a typical 0.35 micron semiconductor fabrication process, VDD is nominally set to 3.3V. A direct current path can therefore be formed between the IO pad 100 and VDD in the presence of a high voltage input at the IO pad 100. There is therefore a need for an ESD protection circuit that can protect circuits in semiconductor chips from high input voltages during normal operations as well as from ESD events. An ESD protection circuit is desirably built with common CMOS components.